TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 517

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

Note 1: The value to be set in I2S0C<WS05:00> must be 16 or larger (18 or larger for I
Note 2: It is recommended that the value to be set in I2S0C<WS05:00> be an even number. Although it is possible to
length is 8 bits and 32 or larger (34 or larger for I
set an odd number, the clock duty of the WS signal does not become 50%. Setting an odd number causes the
High width of the WS signal to become longer by one I2S0CKO pulse than the Low width.
When f
frequency is set as follows:
Based on the above, the transfer clock is set to 400 kbps, and the sampling frequency is
set to 8 kHz in this example.
I2S0CKO = f
•
•
above. A 6-bit counter is provided to divide the transfer clock by 16 to 64. (The
divider value cannot be set to 1 to 15.)
signal can be used as an AD conversion start trigger for the AD converter in this
LSI. Setting I2S0CTL<SYSKE0>=1 and I2S0CTL<CNTE0>=1 enables the WS
signal to be sent to the AD converter. This can be done regardless of the setting of
I2S0CTL<TXE0>.
AD converter.
6-bit counter set value
SYS
The sampling frequency is set by dividing the transfer clock (CK) described
As a special function available only in channel 0, the rising edge of the WS
For details about AD conversion using the WS signal, refer to the chapter on the
Setting the sampling frequency WS
Special function
000000
000001
111111
= 60 MHz, I2S0C<CK07:00> = 150, and I2SnC<WS05:00> = 50, the sampling
= 60 [MHz] / 150 / 50 = 8 [kHz]
SYS
/ 150 / 50
92CF29A-515
2
S transfer) when the data length is 16 bits.
Divider value
64
1
63
2
S transfer) when the data
TMP92CF29A
2009-06-11