IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 102

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Secondary Interrupt COMMON Indication Register
IDT IDT88K8483
TIMEBASE
INDIRECT_ACC R/W
I_FIFO_READY
I_FIFO_OFLOW
O_FIFO_MSG
SOC
10ms
Field
R/W
R/W
R/W
R/W
R/W
R/W
Read /
Write
0:0
0:1
0:2
0:3
0:4
0:5
0:6
Bits
Table 50 Interrupt secondary COMMON indication register (Register Offset=0xe)
Length
1
1
1
1
1
1
1
Reset
0
0
1
0
0
0
0
State
This field indicates an event captured in the timebase.
Read 0: No event is generated.
Read 1: An event is generated by a timebase trigger.
Write 1: Clear the field.
This field indicates an event captured in the indirect access.
Read 0: No event is generated.
Read 1: An event is generated due to an invalid indirect access sequence.
Write 1: Clear the field.
This field indicates when the embedded processor is ready to accept data through the
I_FIFO
Read 0: I_FIFO not ready to accept data.
Read 1: I_FIFO ready to accept data.
Write 1: Resets the field.
This field indicates if the mailbox I_FIFO is oveflowed.
Read 0: No overflow in mailbox I_FIFO.
Read 1: Overflow in mailbox I_FIFO. An attempt to write more than 32 bytes generates
this interrupt.
Write 1: Clears this field.
This field indicates when the embedded processor has data in its mailbox O_FIFO
Read 0: No data in present in O_FIFO.
Read 1: Data is present in O_FIFO.
Write 1: Resets the bit.
SOC trigger
This field generates a 10ms timer event based on the 1ms timer.
Read 0: 10ms timer event is not generated.
Read 1: 10ms timer event is generated.
Write 1: Resets the field.
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Description
October 20, 2006