IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 116
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IDT88K8483
Manufacturer Part Number
IDT88K8483
Description
Spi-4 Exchange Document Issue 1.0
Manufacturer
Integrated Device Technology
Datasheet
1.IDT88K8483.pdf
(162 pages)
- Current page: 116 of 162
- Download datasheet (3Mb)
SPI-4 Egress Calendar Switch Control Register
SPI-4 Egress Fill Level Register
SPI-4 Egress Max Fill Level Register
E_CSW_EN
CAL_ID
E_DIP_CSW
Note: Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for more details about calendar implementation.
FILL_CUR
IDT IDT88K8483
FILL_MAX
There are two registers for SPI-4 main interface.
There are two registers for SPI-4 main interface.
Field
Field
Field
Table 82
Table 84 SPI-4 Egress Max Fill Level Register (Block Base =0x0800, Register Offset = 0x0D and 0x0E)
Table 83 SPI-4 Egress Fill Level Register (Block Base=0x0800, Register Offset = 0x0B and 0x0C)
R/W
R
R/W
R
SPI-4 Egress Calendar Switch Control Register (Block Base = 0x0800, Register Offset=0x08)
R/C
Read /
Read /
Read /
Write
Write
Write
0:0
0:1
0:2
0:0-0:3
0:0-0:3
Bits
Bits
Bits
1
1
1
4
Length
Length
Length
4
0
0
1
0
0
Reset
Reset
Reset
State
State
State
116 of 162
The engress calendar switch enable bit is used to enable the switching of the active
calendars following the reception of the calendar selection word on the status
0:Egress calendar switch is disabled. Only SPI-4 egress calendar 0 is used.
1:Egress calendar switch is enabled. Calendar 0 or calendar 1 will automatically be
selected depending on the value of the received calendar selection words.
MSB of calendar ID word
This field describes the DIP-2 computation method of the received DIP-2 on the sta-
tus channel. It is based on the selection of calendar 0 or calendar 1.Refer to
Table 67 page 110
Indicates the current fill level of the egress locker. Since this is a real-time register,
the value read from it will change rapidly and is used for internal diagnostics only
Indicates the maximum fill level of the egress locker since the time of the last read of
this register. This register is cleared after reading.
channel.
for a detailed explanation.
Description
Description
Description
October 20, 2006
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