IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 92

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Microprocessor Mailbox Output FIFO Length Register
Microprocessor Mailbox Output FIFO Status Register
Embedded Processor State Register
Length
OFIFO_STATUS
EP_READY
EP_RUNNING
CHIP_READY
IDT IDT88K8483
Field
Field
Field
R/W
R
R
R
R
Read /
Read /
Read /
Write
Write
Write
Table 24 Microprocessor Mailbox Output FIFO Length Register
Table 25 Microprocessor Mailbox Input FIFO Status Register
0:0 - 0:5
0:0
0:0
0:1
0:2
Table 26 Embedded Processor State Register
Bits
Bits
Bits
1
6
1
1
1
Length
Length
Length
0
0
0
0
0
Reset
Reset
Reset
State
State
State
92 of 162
The number of data bytes written to the “data” field in the
Output FIFO Data Register (p.
Indicates whether the host CPU(READ side) or IDT88K8483 (WRITE side) has con-
trol of OFIFO.
0: IDT88K8483 (WRITE side) has control of IFIFO.
1: Host CPU(READ side) has control of IFIFO.
This flag indicates whether the chip is ready to download the firmware binary file
from the host CPU. This flag is checked before the host CPU downloads to the
IDT88K8483. This bit is cleared by reset and will go high after the chip is initialized.
0:Not ready for download.
1:Ready for application s/w download.
This flag indicates whether the downloading procedure is finished.
0:Download taking place.
1:Download finished.
This bit indicates that the downloaded software has initiated the chip and user can
access it. This bit is set by downloaded software and is cleared by reset.
0:Chip not yet ready.
1:Chip is ready to be used.
(Register Offset=0x16)
(Register Offset=0x15)
(Register Offset=0x13)
91), by the IDT88K8483.
Description
Description
Description
Microprocessor Mailbox
October 20, 2006