IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 31

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
WRB/SDI
RDB / SCLK
CSB
INTB
SPIEN
MPM
JTAG Interface
TRSTB
TCK
TMS
TDO
TDI
Miscellaneous Interface
RESETB
TESTSE
TIMEBASE
GPIO[2:0]
Clock Interface
SPI4A_RCLK
SPI4B_RCLK
SPI4M_RCLK
DIV4
Symbol
1
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Schmitt Trigger
Schmitt Trigger
Schmitt Trigger
Schmitt Trigger
Schmitt Trigger
Open Drain
Pull-down
Pull-down
Type
tri-state
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
CMOS
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
CMOS
CMOS
Pull-up
CMOS
CMOS
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
CMOS
Pull-up
2
WRB is Microprocessor Write Control. Active low.
SDI is Serial Peripheral Interface (SPI) Chip Select. Active low.
RDB is Microprocessor Read Control. Active low.
SCLK is Serial Peripheral Interface (SPI) Clock.
CSB is Microprocessor Chip Select. Active low.
INTB is Microprocessor Interrupt. Active low.
SPIEN is Serial Peripheral Interface (SPI) mode enable. Active high.
MPM is Microprocessor mode Control. This signal controls the micro-
controller mode. 1 - Intel Mode. 0 - Motorola Mode.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and the JTAG TAP Controller. An external pull-up on the
board is recommended to meet the JTAG specification in cases where
the tester can access this signal.
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller.
JTAG Mode. The value on this signal controls the test mode select of
the boundary scan logic or JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller.
JTAG Data Input. This is the serial data input to the boundary scan logic
or JTAG Controller.
Hardware Reset. Active low.
Test Scan Enable. Active high. Input used for IDT factory test. This sig-
nal should be pulled down for normal operation.
Time Base. A positive edge on this signal updates the PMON counters.
Subsequent edges within approximately 4ms are be ignored.
General Purpose I/O. These pins can be configured as general purpose
I/O pins.
Interface A/B/M Reference Clock.
Pre-scalar Select. Configuration pin.
Table 2 Pin Description (Part 4 of 5)
31 of 162
Function
Comments
October 20, 2006