IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 42

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Ingress Data Channel
tion and transfer termination. The status channel generates status frame, and controls the output skew per lane.
IDT IDT88K8483
The SPI-4 ingress data channel is independent from the status channel. The data channel supports bit alignment and de-skew, error event detec-
SPI4A_ESTA[1:0]_N
SPI4A_ESTA[1:0]_P
SPI4A_ED[15:0]_P
SPI4A_ED[15:0]_N
SPI4A_ISTA[1:0]_P
SPI4A_ISTA[1:0]_N
SPI4A_ID[15:0]_N
SPI4A_ID[15:0]_P
SPI4A_EDCLK_N
SPI4A_ESCLK_N
SPI4A_ESCLK_P
SPI4A_EDCLK_P
SPI4A_IDCLK_N
SPI4A_LVDSSTA
SPI4A_IDCLK_P
IDT88K8483
SPI4A_ISCLK_P
SPI4A_ISCLK_N
SPI4A_ECTL_N
SPI4A_ECTL_P
SPI4A_ICTL_N
SPI4A_ICTL_P
SPI4A_VREF
SPI4A_BIAS
Figure 14 IDT88K8483 SPI-4 Connections Example
3K 1%
V
V
DDL12
DDL25
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SPI4A_IDCLK_P
SPI4A_ICTL_N
SPI4A_ISTA[1:0]_P
SPI4A_IDCLK_N
SPI4A_ISTA[1:0]_N
SPI4A_ISCLK_P
SPI4A_ED[15:0]_P
SPI4A_ECTL_P
SPI4A_ESTA[1:0]_N
SPI4A_ISCLK_N
SPI4A_ED[15:0]_N
SPI4A_EDCLK_P
SPI4A_EDCLK_N
SPI4A_ECTL_N
SPI4A_ESTA[1:0]_P
SPI4A_ESCLK_P
SPI4A_ID[15:0]_P
SPI4A_ID[15:0]_N
SPI4A_ICTL_P
SPI4A_ESCLK_N
Network Processor
October 20, 2006