IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 129

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Auxiliary Registers
Auxiliary Interface Enable Register
Auxiliary Interface Configuration Register
Auxiliary Extension Buffer Configuration Register
AUX_EN
AUX_PDN
MEM
LIDMDF
EBC[2:0]
IDT IDT88K8483
Field
Field
Field
Note:
Note:
1
1
Table 118 Auxiliary Extension Buffer Configuration Register (Block Base=0x0A00, Register Offset=0x02)
2
The interface has to be configured before enabling it.This is done in Auxiliary Interface Configuration Register (p. 129)
The interface has to be powered down before configuring it to the QDR II interface mode or the generic interface mode
The interface has to be powered down before configuring it to the QDR-II interface mode or the generic interface mode
Table 117 Auxiliary Interface Configuration Register
R/W
R/W
R/W
R/W
R/W
Read /
Read /
Read /
Write
Write
Write
Table 116 Auxiliary Interface Enable Register (Block Base=0x0A00, Register Offset=0x00)
0:0
0:1
0:0
0:2
0:1
Bits
Bits
Bits
1
1
1
1
3
Length
Length
Length
0
0
0
0
0
Reset
Reset
Reset
State
State
State
129 of 162
This field enables the auxiliary interface
0:Disable the auxiliary interface.
1:Enable the auxiliary interface.
This field powers down the auxiliary outputs except for the clock.
0:Power up the auxiliary interface.
1:Power down the auxiliary interface.
This bit configures the auxiliary interface to QDR-II mode or generic mode
0: Generic interface mode.
1: QDR-II interface mode.
This bit defines the manner in which the LID in the PFP is mapped to the FIFOs in
the QDR-II, for both status channel and data channel.
0: PFP LID x status channel is mapped to FIFO x status channel in the external
QDR-II SRAM. FIFO x data channel in the QDR-II SRAM is mapped to the PFP LID
x data channel. This setting is used when all PFP LID channels are mapped to
QDR-II FIFOs.
1: PFP LID x status channel is mapped to the (FIFO x - LID_offset) status channel in
the external QDR-II SRAM. FIFO x data channel in the QDR-II SRAM is mapped to
the PFP (LID x+ LID_offset) data channel. This setting is used when some LIDs are
mapped to the QDR-II FIFOs and other LIDs are mapped to the egress interface.
Determines the number of FIFOs that are configured in the external QDR-II SRAM.
Please refer to Table 119 for more information.
(Block Base=
0x0A00
, Register Offset=0x01)
Description
Description
Description
1
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October 20, 2006
1
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