IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 91

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IDT88K8483

Manufacturer Part Number
IDT88K8483
Description
Spi-4 Exchange Document Issue 1.0
Manufacturer
Integrated Device Technology
Datasheet
Microprocessor Mailbox Input FIFO Status Register
Microprocessor Mailbox Output FIFO Data Register
IFIFO_STATUS
Data
IDT IDT88K8483
Field
Field
R
R/W
Read /
Read /
Write
Write
Table 23 Microprocessor Mailbox Output FIFO Data Register
Table 22 Microprocessor Mailbox Input FIFO Status Register
0:0 - 0:7
0:0
Bits
Bits
1
8
Length
Length
0
0
Reset
Reset
State
State
91 of 162
This field indicates whether the host CPU (WRITE side) or the IDT88K8483 (READ
side) has control of the mailbox input IFIFO.
0:Host CPU (WRITE side) has control of IFIFO. Also indicates that the mailbox input
FIFO is empty and data can be written to the FIFO by the host.
1:IDT88K8483 (READ side) has control of IFIFO.
Data is written/downloaded to this field, which is a 32 byte OFIFO, by the
IDT88K8483 and read by the host CPU.
(Register Offset=0x14)
(Register Offset=0x12)
Description
Description
October 20, 2006

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