IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 48

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 1, then the DIP-2 is computed over calendar selection word and all preceding status indi-
cations after last ‘11’ framing pattern. If E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 0, then the DIP-2 is computed over all preceding
status indications after last ‘11’ framing pattern, excluding the calendar selection word.
fied’. In IN_SYNCH state, the status is updated per cycle rather than updated all LP at the end of the frame. In OUT_OF_SYNCH state, the calendar’
LP’s status are fixed to ‘satisfied’. In the two-calendar modes, the MSB of calendar ID is extracted to CAL_ID field in
Control Register (p.
E_CAL_LEN field can be programmed with any value. In LVDS mode, the E_CAL_LEN field must be programmed with 4n-1 (n is an integer).
No status channel option
No status mode, the Egress synchronization is fixed at out of sync, there is no DIP-2 error check, and per LP status is fixed to ‘starving’.
Diagnose features
4 Egress Status Register (p. 115)
the device detects “no transition” on the LVDS input clock.
E_DIP_NUM field in the
set to 1, error insertion is triggered using the E_DIP_NUM field value.The E_ERR_INS field is self cleared when the correct number of errors is gener-
ated. The E_DIP_NUM field value is user-configured and is not changed internally.
Register (p. 115)
maximum port buffer fill level is configured by using the FILL_MAX field in the
Insert and Extract paths
OBC insert/extract path
IDT IDT88K8483
If the E_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after last ‘11’ framing pattern. If
In IN_SYNCH state, each DIP-2 error generates a DIP-2 error event towards to PMON. A single DIP-2 error sets all calendar LP’s status to ‘satis-
There is an option to configure the device to no status channel mode by the NO_STAT field in the
- Egress status channel clock detect. If there is no transition on MCLK clock in a 2048 MCLK hopping window, then the SLCK_AV field in the
- DIP-4 error insertion. A number of consecutive (less than 16) DIP-4 errors can be generated. The number of error is configured by the
- Force continuous training. The data channel generates continuous training pattern if E_FORCE_TRAIN field in the
- Egress port Buffer fill level. The egress Port Buffer fill level is indicated in the FILL_CUR field in the
A useful feature for diagnostics is the OBC (On Board Controller) insert and extract path.
The calendar length is configured in the E_CAL_LEN field in the
is set to 1.
116). The CAL_ID field does not change in single calendar mode or in out of sync state.
SPI-4 Egress Diagnostics Register (p.
is cleared to 0. The SLCK_AV field transition from 1 to 0 generates an event forward to PMON. In LVDS I/O mode,
115). When the E_ERR_INS field in the
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SPI-4 Egress Calendar 0 Configuration Register (p.
SPI-4 Egress Max Fill Level Register (p.
SPI-4 Egress Configuration Register (p.
SPI-4 Egress Diagnostics Register (p. 115)
SPI-4 Egress Fill Level Register (p.
SPI-4 Egress Calendar Switch
116).
SPI-4 Egress Diagnostics
114). In LVTTL mode, the
October 20, 2006
116). The
113). In
SPI-
is