IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 110

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Ingress Fill Level Register
SPI-4 Ingress Max Fill Level Register
FILL_CUR
FILL_MAX
IDT IDT88K8483
There are 2 registers for SPI-4 main interface.
There are 2 registers for SPI-4 main interface.
Field
Field
0
1
X
I_DIP_CSW
X
1
0
CAL_SEL
Table 69
Table 68
R
R/Clear
Read /
Read /
Write
Write
SPI-4 Ingress Max Fill Level Register (Block Base=0x0300, Register Offset=0x0D-0x0E
0
1
1
I_CSW_EN
SPI-4 Ingress Fill Level Register (Block base=0x0300, Register offset=0x0B-0x0C)
1
1
0
I_CSW_EN
0:0-0:5
0:0-0:5
Bits
Bits
DIP2 is computed over all preceding status indications after last ‘11’ framing pattern.
DIP2 is computed over all preceding status indications after last ‘11’ framing pattern, including the
calendar selection word, which is fixed at 10b.
DIP2 is computed over all preceding status indications after last ‘11’ framing pattern, excluding the
calendar selection word.
Table 67 Ingress calendar Switch Register: Bit I_DIP_CSW
Table 66 Ingress Calendar Switch Register: Bit CAL_SEL
6
6
Length
Length
Selects Calendar 0.Calendar selection word is fixed to 01b and is placed after framing pattern.
Selects Calendar 1.Calendar selection word is fixed to 10b and is placed after framing pattern.
Selects Calendar 0.
0x0
0x0
Reset
Reset
State
State
110 of 162
Indicates the current fill level of the ingress locker. Since this is a real-time register,
the value read from it will change rapidly and is used for internal diagnostics only.
Indicates the maximum fill level of the ingress locker since the time of the last read
of this register. This register is cleared after reading.
Description
Description
Description
Description
October 20, 2006