IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 55

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

QDR-II Interface
Overview
configured by the MEM field in the
is enabled. The auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the AUX_PDN field in the
Enable Register (p.
36 bits output data bus (four bytes) and 18 bits address bus. The 36 bits data bud include 32 bits payload data and 4 bits overhead. The interface has
also QDR_K and QDR_KB output clocks and QDR_CQ and QDR_CQB input clocks. The device supports up to 64 independent FIFOs in the memory,
and a full duplex 10Gbps data-stream to and from the memory. It also supports flow control per LID.
MAX1510 as shown in
QDR-II Transfer format
format. The format adds 4 overhead bits to each 32 payload bits group. The transfer format overhead includes the total length of the payload (in units
of bytes), packet delineation and error tags. The first two overhead fields of a transfer format contain the higher bit of the transfer length, and the
transfer beginning field. The third overhead field contains packet delineation and error tag. The fourth overhead field contains the last two bits of the
transfer length. All the remaining overhead fields are fixed to 0’b0000.
integer multiple of 2 words (36 bit).
Memory segmentation
Auxiliary Interface Configuration Register (p.
IDT IDT88K8483
The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is
The QDR-II interface can be connected to 18M bit QDR-II burst of two SRAM with 36 bit data at 200 MHz. The interface has 36 bits input data bus,
The QDR_VREF signal should be connected to 0.75V generated from the VDDH15 power supply using regulator or potential divider such as the
In a single write burst a transfer with 1 to 256 bytes is stored in the memory. A format is defined to map the 1 to 256 bytes in a proprietary transfer
The minimum length of the transfer format is 4 words (36 bit). The payload is padded with a fixed 0xFF pattern. The transfer length is equal to an
The external SRAM is segmented in a configurable number of FIFOs with equal size. The number of the FIFOs is configured by EBC field in the
129). The interface is enabled by setting to 1 the AUX_EN field in the
Figure 42 IDT88K8483 VDDA25 Filter Circuit
IDT88K8483
Auxiliary Interface Configuration Register (p.
QDR_D[35:0]
QDR_Q[35:0]
QDR_A[17:0]
QDR_VREF
QDR_CQB
QDR_IMP
QDR_WR
QDR_KB
QDR_CQ
QDR_RB
QDR_K
Figure 23 IDT88K8483 and IDT7172604 QDR-II SRAM connections
129). The memory is managed based on memory segment size of 256byte.
V
DDH15
100 OHM
/2
55 of 162
p.75.
129). The auxiliary interface has to be configured before the interface
CQ
D[35:0]
SA[35:0]
Q[35:0]
K
CQ
R
W
K
18Mb burst of 2
Auxiliary Interface Enable Register (p.
QDRII SRAM
IDT7172604
October 20, 2006
129).
Auxiliary Interface