IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 104

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Indirect Registers Description
MCLK Divider Sticky Register
Clock Control Input Status Register
Clock Registers
N
block.Please
DIV_FOUR
CK_SEL_A
CK_SEL_B
CK_SEL_M
Note: Please refer to
IDT IDT88K8483
Field
Field
Note: (1) All indirect registers are 32 bits wide.
Note: (1) “Sticky” means that the register value does not change during software reset.
(2) Treat unused bits as reserved bits.
(3) A READ to unused/reserved bits returns 0 while a WRITE is ignored.
refer to Figure 36 Clock Generator Type M p.70“Clock Generator Type M” on page 70 for MCLK discussion.
CLK_SEL signals configuration (p. 69)
Table 53
R/W
R
R
R
R
Read /
(2) MCLK is generated by the clock generator type M and is used for generic interface, the PFP block and the PMON
Read /
Write
Write
Table 52
Clock Control Input Status Register (Block Base=0x0a00, Register Offset=0x01)
MCLK Divider Sticky Register (Block Base=0x0a00, Register Offset=0x00)
0:0-0:1
0:0
0:1
0:2
0:3
Bits
Bits
2
1
1
1
1
Length
Length
and
11
Pin input
Pin input
Pin input
Pin input
Figure 36 Clock Generator Type M p.70
Reset
Reset
State
State
104 of 162
Selects the frequency of the MCLK.
00: F/2.
01: F/3.
10: F/4.
11: F/5.
Reflects the state of the external configuration signal DIV4. This signal selects the
prescaler frequency to divide by 1 or 4.
0: Configures the prescaler frequency to divide by 1. Full rate.
1: Configures the prescaler frequency to divide by 4. Quarter rate.
Reflects the value of the external configuration signal SPI4A_CLK_SEL. This signal
configures the divider1 frequency to divide by 2 or 8.
0: Divide by 2.
1: Divide by 8.
Reflects the value of the external configuration signal SPI4B_CLK_SEL. This signal
configures the divider1 frequency to divide by 2 or 8.
0: Divide by 2.
1: Divide by 8.
Reflects the value of the external configuration signal SPI4M_CLK_SEL. This signal
configures the divider1 frequency to divide by 2 or 8.
0: Divide by 2.
1: Divide by 8.
for clock description.
Description
Description
October 20, 2006