IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 141

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

PMON Buffer M-T Overflow Indication Register
PMON Buffer T-M Overflow Interrupt Control Register
PMON Buffer M-T Overflow Interrupt Control Register
OVERFLOW[31:0]
OVF_EN[31:0]
OVF_EN
IDT IDT88K8483
There are 2 registers.
There are 2 registers.
There are 2 registers.
Field
Field
Field
Table 143 PMON Buffer T-M Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x06-0x07)
Table 144 PMON Buffer M-T Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x08-0x09)
Table 142 PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05)
R/W
R/W
R/W
Read /
Read /
Read /
Write
Write
Write
0:0-3:7
0:0-3:7
0:0-3:7
Bits
Bits
Bits
32
32
32
Length
Length
Length
0
0
0
Reset
Reset
Reset
State
State
State
141 of 162
This register indicates the overflow on a per LID basis from the main to tributary
SPI-4 interface. Bit 0 of register with offset 0x04 indicates overflow for LID 0, bit 3
for LID 3, bit 0 of 2nd register with offset 0x05 indicates overflow for LID 32 and so
on.
Read 1: Indicates overflow for that LID.
Read 0: Indicates no overflow for that LID.
Write 1: Clears the bit.
This register enables or disables the overflow indication for the LIDs which is
indicated in registers in
bit 0 of register with offset 0x07 is for LID 32 and so on.
0: Disables overflow indication in PMON buffer T-M overflow indication register.
1: Enables overflow indication in PMON buffer T-M overflow indication register.
This register enables or disables the overflow indication for the LIDs which is
indicated in registers in
bit 0 of register with offset 0x09 is for LID 32 and so on.
0: Disables overflow indication in PMON buffer M-T overflow indication register.
1: Enables overflow indication in PMON buffer M-T overflow indication register.
Table
Table
141.Bit 0 of register with offset 0x06 is for LID 0 and
142.Bit 0 of register with offset 0x08 is for LID 0 and
Description
Description
Description
October 20, 2006