IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 111

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Ingress WATERMARK Register
SPI-4 Ingress Training to out of sync threshold Register
SPI-4 Egress LID To LP Mapping Table
SPI-4 Egress Calendar 0 Table
channel LPs to the attached device
WATERMARK
Note:(1) 0x1F is the highest watermark that can be set, meaning that the ingress buffer will be full before backpressure will be initiated on a SPI-4 ingress inter
STRT_TRAIN
LP
EN
LP
IDT IDT88K8483
There are 2 registers for SPI-4 main interface.
There are 128 table entries for SPI-4 main interface and 64 table entries for SPI-4 tributary interface.
There are 128 table entries for SPI-4 main egress and 64 table entries for SPI-4 tributary egress calendar_0 to schedule the updating of the status
(2) Per LID backpressure is set in fields THR_STARV and THR_HUNG in the
Field
Field
Field
Field
face PFP. A WATERMARK field value of 0x0F is used to set a watermark for a half-full ingress buffer before tripping backpressure.
Note: The LID number is equal to the register offset.
Table 72
Table 71
Table 73
Table 70
R/W
SPI-4 Egress LID To LP Mapping Table (Block Base=0x0400, Register Offset=0x00-0x3F/0x7F)
R/W
R/W
R/W
R/W
Read /
Read /
Read /
Read /
Write
Write
Ingress Training to out of sync threshold Registe(Block Base=0x0300,Register Offset=0x13)
Write
Write
SPI-4 Egress Calendar 0 Table (Block Base=0x0500, Register Offset=0x00-0x3F/0x7F)
SPI-4 Ingress Watermark Register (Block Base=0x0300, Register Offset=0x0F-0x10)
0:0-0:4
0:0-0:7
1:0
0:0-0:7
0:0-0:7
Bits
Bits
Bits
Bits
5
8
1
8
Length
Length
Length
8
Length
0x0d
0
0
0xFF
Reset
Reset
Reset
State
State
State
111 of 162
0
Sets the watermark value per PFP.This indicates that if “WATERMARK” number of
ingress lockers are full, then backpressure will be initiated for all LIDs on a SPI-4
ingress interface.
LP number. LID to LP map is used to map a LID used internally to a SPI-4 egress
logical port.
The EN bit is used to enable or disable the connection of a LID to an LP.
0=LP is disabled
1=LP is enabled
The Logical Port value programmed in this field, schedules a status channel update
according to the calendar sequence.
Reset
State
PFP Buffer Segment Assign Table (p. 120)
!=0: If this field is not equal to zero, then the ingress interface
goes out of sync if more than STRT_TRAIN times consecutive
training pattern is received on its data channel.
Description
Description
Description
Description
October 20, 2006