IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 69

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Clock
generators (tributary A and tributary B) are type T. There are three input clocks SPI4A_RCLK, SPI4B_RCLK and SPI4M_RCLK. Each one of the clock
inputs is a clock source to one of the three internal clock generators. The device also has 4 clock configuration signals (DIV4, SPI4A_CLK_SEL,
SPI4B_CLK_SEL, and SPI4M_CLK_SEL) for programing the clock generators. The clock generator type M includes the following blocks: Prescaler,
PLL and three independent dividers as described in
following blocks: Prescaler, PLL and two independent dividers as described in
as described in
CK_SEL_B and CK_SEL_C fields in the
frequency to divide by 4 or 1 as described in
Status Register (p.
IDT IDT88K8483
IDT88K8483 has three programmable clock generators (main, tributary A and tributary B). One clock generator (main) is type M and two clock
The external configuration signals SPI4A_CLK_SEL, SPI4B_CLK_SEL and SPI4M_CLK_SEL configure the Divider 1 frequency to divide by 2 or 8
SPI4A_CLK_SEL, SPI4B_CLK_SEL,
(external input signal:
SPI4M_CLK_SEL)
Table
(external input signal)
104).
CKSEL
9. The external signals SPI4A_CLK_SEL, SPI4B_CLK_SEL and SPI4M_CLK_SEL value are reflected by CK_SEL_A,
0
1
TIM EBASE interrupt
DIV4
Tim ebase trigger
0
1
Clock Control Input Status Register (p.
Table
10. The external signal DIV4 value is reflected by DIV_FOUR field in the
Figure 36 Clock Generator Type M
Table 9 CLK_SEL signals configuration
RCLK / 1 (RCLK is external input signal:
RCLK / 4 (RCLK is external input signal:
Figure 35 External PMON Time Base
Table 10 DIV4 signal configuration
(external output signals)
plloclk / 2 (plloclk is internal signal)
plloclk / 8 (plloclk is internal signal)
3-4m s for PM O N updating
SPI4A_RCLK, SPI4B_RCLK,
SPI4A_RCLK, SPI4B_RCLK,
EDCLK / ISCLK_T
(internal signal)
SPI4M_RCLK)
SPI4M_RCLK)
69 of 162
pllrclk
Figure 37 Clock Generator Type T
104). The external configuration signal DIV4 configures the prescaler
p.70. The clock generators type T include the
Operation Mode
Quarter rate
Operation Mode
Full rate
Quarter rate
Full rate
p.70.
October 20, 2006
Clock Control Input