IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 145

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Miscellaneous Registers
PMON Timebase Control Register
PMON 1ms Timer Register
GPIO Direction Register
INTERNAL
TIMER
MANUAL
PERIOD
DIR_OUT
IDT IDT88K8483
There are 3 registers.Register offset 0x10 is for GPIO 0. Register offset 0x11 is for GPIO 1and register offset 0x12 is for GPIO 2.
Field
Field
Field
R/W
R/W
R/WC
R/W
R/W
Read /
Read /
Read /
Write
Write
Write
Table 159
Table 156
Table 158
X
X
X
Manual
GPIO Direction Register (Block Base=0x8B00, Register Offset=0x10-0x12)
PMON Timebase Control Register
0:0
0:1
0:2
0:0-2:1
0:0
Bit 2
Bits
Bits
Bits
PMON 1ms Timer Register
1
1
1
18
1
Length
Length
Length
X
1
0
Timer
Bit 1
Table 157 Timebase source table.
0
0
0
0x1E600
0
Reset
Reset
Reset
State
State
State
145 of 162
0
1
1
Selects between the internal and external time base.Please refer to table 144.
Selects the internal timer/OBC as the timebase timing source. Please refer to table
144.
Manual time base trigger, self clear.
The timer register specifies the number of MCLK for generation of a 1ms time
interval.
This field controls the direction of General Purpose IO pins. The direction can be
input or output.
0: The GPIO pins act as input/read pins.
1: The GPIO pins act as output/write pins.
(Block Base=0x8B00, Register Offset=0x01)
Internal
Bit 0
(Block Base=0x8B00, Register Offset=0x00)
External.
Internal timer.
External OBC.
Timebase trigger
Source
Description
Description
Description
October 20, 2006