IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 28

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Pin Description Table
are defined as being negative. Digital signals ending with “B” are defined as being active, or asserted, when at a logic zero (low) level. All other digital
signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT IDT88K8483
The following table lists the functions of the pins provided on the IDT88K8483. Some of the functions listed are multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Analog signals ending with “P” are defined as being positive. Analog signals ending with “N”
SPI-4 Interface
SPI4A_ED[15:0]_P
SPI4B_ED[15:0]_P
SPI4M_ED[15:0]_P
SPI4A_ED[15:0]_N
SPI4B_ED[15:0]_N
SPI4M_ED[15:0]_N
SPI4A_EDCLK_P
SPI4B_EDCLK_P
SPI4M_EDCLK_P
SPI4A_EDCLK_N
SPI4B_EDCLK_N
SPI4M_EDCLK_N
SPI4A_ECTL_P
SPI4B_ECTL_P
SPI4M_ECTL_P
SPI4A_ECTL_N
SPI4B_ECTL_N
SPI4M_ECTL_N
SPI4A_ESTA[1:0]_P
SPI4B_ESTA[1:0]_P
SPI4M_ESTA[1:0]_P
SPI4A_ESTA[1:0]_N
SPI4B_ESTA[1:0]_N
SPI4M_ESTA[1:0]_N
SPI4A_ESCLK_P
SPI4B_ESCLK_P
SPI4M_ESCLK_P
SPI4A_ESCLK_N
SPI4B_ESCLK_N
SPI4M_ESCLK_N
SPI4A_ESTA_T[1:0]
SPI4B_ESTA_T[1:0]
SPI4M_ESTA_T[1:0]
SPI4A_ESCLK_T
SPI4B_ESCLK_T
SPI4M_ESCLK_T
Symbol
1
I/O
O
O
O
I
I
I
I
Schmitt Trigger
Type
LVTTL
Pull-up
LVTTL
Pull-up
LVDS
LVDS
LVDS
LVDS
LVDS
2
Egress Data Bus. This data bus is used to carry egress payload data
and in-band control words.
Egress Data Clock. This clock is associated with the egress data bus
(ED) and the control signal (ECTL).
Egress Control. This signal is high when a control word is present on
the egress data bus (ED) and it is low otherwise.
Egress FIFO Status LVDS. These signals are used to carry egress
round-robin FIFO status information, along with associated error detec-
tion and framing.
Egress Status Clock LVDS. This clock is associated with the egress
FIFO status signals (ESTA).
Egress FIFO Status LVTTL. These signals are used to carry egress
round-robin FIFO status information, along with associated error detec-
tion and framing.
Egress Status Clock LVTTL. This clock is associated with the egress
FIFO status signals (ESTA_T).
Table 2 Pin Description (Part 1 of 5)
28 of 162
Function
TDAT[15:0]
TDCLK
TCTL
TSTAT[1:0]
TSCLK
TSTAT[1:0]
TSCLK
Link
Comments
October 20, 2006
RDAT[15:0]
RDCLK
RCTL
RSTAT[1:0]
RSCLK
RSTAT[1:0]
RSCLK
PHY