IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 41

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Interface
Overview
processor), for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications. The SPI-4.2
protocol transfers data in variable length bursts. Associated with each burst is information such as logical port number (for a multi-port device such as
a 10 x 1 GbE MAC), SOP, EOP. This information is collected by the SPI-4 interface and passed to the PFPs. The Optical Internetworking Forum (OIF)
controls the SPI-4.2 Implementation Agreement document (available at http://www.oiforum.com).
interface is enabled. The SPI-4 interface LVDS outputs (except for the clock) can be powered down by setting to 1 the SPI4_PDN field in the
Interface Enable Register (p.
Example
signal, all of which use LVDS (differential) signaling, and are sampled on both edges of the clock. There are also ingress status port and egress status
port. Each status port has 2 fifo status signals and a clock. The status port signal can be configured to LVDS (differential) or LVTTL by the status
channel control pin
port supports programmable skew.
face supports up to 64 logical ports. The main SPI4 interface supports up to 128 logical ports. The logical port in-band address are from 0 to 255.
SPI4B_IDCLK_N, SPI4M_IDCLK_P and SPI4M_IDCLK_N). The source clock for the SPI-4 egress port is the internal SPI-4 clock generator.
IDT IDT88K8483
SPI-4.2 as originally defined is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device (network
The SPI-4 interface power down mode has to be disabled before configuring the interface. The SPI-4 interface also has to be configured before the
The SPI-4 interface consists of separate ingress and egress interfaces as described in
The IDT88K8483 has three SPI-4 interfaces: one main SPI-4 interface (M) and two tributary SPI-4 interface (A and B). Each tributary SPI4 inter-
The clock source for the SPI-4 ingress port is the SPI-4 interface input clock IDCLK (SPI4A_IDCLK_P, SPI4A_IDCLK_N, SPI4B_IDCLK_P,
p.42. The ingress and egress ports are unidirectional and independent of each other. Each port has 16 data signals, a clock, and a control
LVDSSTA (SPI4A_LVDSSTA, SPI4B_LVDSSTA, SPI4AM_LVDSSTA)
106). The interface is enabled by setting to 1 the SPI4_EN field in the
41 of 162
. The ingress port supports dynamic alignment, and the egress
Figure 14 IDT88K8483 SPI-4 Connections
SPI-4 Interface Enable Register (p.
October 20, 2006
106).
SPI-4