XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 18

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Signals
There are two kinds of pins that are used to configure
Spartan-II devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an
input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a V
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
"Pinout Tables"
FPGA Series Configuration and Readback.
The Process
The sequence of steps necessary to configure Spartan-II
devices are shown in
divided into three different phases.
•
•
•
•
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration
process: applying power to the device or asserting the
PROGRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in
begin, V
Furthermore, all V
2.5V supply. For more information on delaying
configuration, see
page
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process
DS001-2 (v2.8) June 13, 2008
Product Specification
Initiating Configuration
Configuration memory clear
Loading data frames
Start-up
19.
CCO
Figure 12, page
R
Bank 2 must be greater than 1.0V.
in Module 4 and XAPP176, Spartan-II
CCINT
"Clearing Configuration Memory,"
Figure
power pins must be connected to a
19. Before configuration can
11. The overall flow can be
CCO
of 3.3V to drive
www.xilinx.com
by driving DONE Low, then enters the memory-clearing
phase.
Spartan-II FPGA Family: Functional Description
Figure 11: Configuration Flow Diagram
Configuration
at Power-up
V
High?
V
AND
CCINT
CCO
Yes
FPGA Drives DONE High,
Start-up Sequence
Releases GSR net
and DONE Low
User Operation
Activates I/Os,
Configuration
Configuration
Data Frames
User Holding
Drives INIT
User Holding
Mode Pins
No
PROGRAM
Correct?
Samples
Memory
No
FPGA
FPGA
Clear
Load
CRC
Low?
Low?
INIT
No
Yes
No
Yes
Yes
Configuration During
User Operation
PROGRAM
Abort Start-up
User Pulls
FPGA Drives
INIT Low
Delay
Configuration
Delay
Configuration
Low
DS001_11_111501
Module 2 of 4
18