XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 46

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

SSTL3 Class I
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in
appear in
Specifications"
characteristics.
Table 25: SSTL3_I Voltage Specifications
DS001-2 (v2.8) June 13, 2008
Product Specification
Notes:
1.
2.
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
V
V
≤ V
at V
SSTL3 Class I
≥ V
at V
= V
≤ V
≥ V
IH
IL
= 0.45 × V
V
minimum does not conform to the formula.
maximum is V
CCO
REF
OL
REF
REF
OH
REF
REF
Figure 47: Terminated SSTL3 Class I
Table 25
Parameter
(mA)
R
= 3.3V
(mA)
+ 0.2
– 0.2
+ 0.6
– 0.6
in Module 3 for the actual FPGA
CCO
25Ω
for the SSTL3_I standard. See
Figure
CCO
+ 0.3.
47. DC voltage specifications
Z = 50
V
REF
–0.3
Min
= 1.5V
3.0
1.3
1.3
1.5
1.9
50Ω
–8
V
8
-
TT
(2)
= 1.5V
DS001_47_061200
Typ
3.3
1.5
1.5
1.7
1.3
-
-
-
-
"DC
3.9
Max
3.6
1.7
1.7
1.5
1.1
www.xilinx.com
-
-
-
(1)
SSTL3 Class II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in
appear in
Specifications"
characteristics.
Table 26: SSTL3_II Voltage Specifications
Notes:
1.
2.
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
V
V
≤ V
at V
SSTL3 Class II
≥ V
at V
= V
≤ V
≥ V
IH
IL
= 0.45 × V
V
minimum does not conform to the formula
Spartan-II FPGA Family: Functional Description
maximum is V
CCO
REF
REF
OL
REF
OH
REF
Figure 48: Terminated SSTL3 Class II
REF
Table 26
Parameter
(mA)
= 3.3V
(mA)
+ 0.2
– 0.2
+ 0.8
– 0.8
in Module 3 for the actual FPGA
25Ω
CCO
for the SSTL3_II standard. See
50Ω
V
CCO
Figure
TT
= 1.5V
+ 0.3
48. DC voltage specifications
Z = 50
V
REF
–0.3
= 1.5V
Min
–16
50Ω
3.0
1.3
1.3
1.5
2.1
V
16
-
TT
(2)
= 1.5V
DS001_48_061200
Typ
3.3
1.5
1.5
1.7
1.3
Module 2 of 4
-
-
-
-
"DC
3.9
Max
3.6
1.7
1.7
1.5
0.9
-
-
-
(1)
46