XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 27

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Design Considerations
This section contains more detailed design information on
the following features:
•
•
•
Using Delay-Locked Loops
The Spartan-II FPGA family provides up to four fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits that improve and
simplify system level design.
Introduction
Quality on-chip clock distribution is important. Clock skew
and clock delay impact device performance and the task of
managing clock skew and clock delay with conventional
clock trees becomes more difficult in large devices. The
Spartan-II family of devices resolve this potential problem
by providing up to four fully digital dedicated on-chip
Delay-Locked Loop (DLL) circuits which provide zero
propagation delay and low clock skew between output clock
signals distributed throughout the device.
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network
minimizes clock skews due to loading differences. By
monitoring a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the
individual clock loads within the device.
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at
100 MHz. This technique can simplify board design
because the clock path on the board no longer distributes
such a high-speed signal. A multiplied clock also provides
designers the option of time-domain-multiplexing, using one
circuit twice per clock cycle, consuming less area than two
copies of the same circuit.
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
DS001-2 (v2.8) June 13, 2008
Product Specification
Delay-Locked Loop . . . see
Block RAM . . . see
Versatile I/O . . . see
R
page 32
page 36
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www.xilinx.com
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance
clocks.
Library DLL Primitives
Figure 22
BUFGDLL. This macro delivers a quick and efficient way to
provide a system clock with zero propagation delay
throughout the device.
two library DLL primitives. These primitives provide access
to the complete set of DLL features when implementing
more complex applications.
Figure 24: High-Frequency DLL Primitive CLKDLLHF
Figure 22: Simplified DLL Macro BUFGDLL
Figure 23: Standard DLL Primitive CLKDLL
Spartan-II FPGA Family: Functional Description
shows the simplified Xilinx library DLL macro,
I
CLKIN
CLKFB
CLKIN
CLKFB
RST
RST
0 ns
Figure 23
CLKDLLHF
CLKDLL
and
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK180
CLKDV
LOCKED
Figure 24
DS001_23_032300
DS001_22_032300
O
DS001_24_032300
Module 2 of 4
show the
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