XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 64

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
Combinatorial Delays
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Set/Reset
T
T
T
F5INCK
T
T
IF5CK
IF6CK
T
CECK
A zero hold time listing indicates no hold time or a negative hold time.
T
DICK
RCK
T
Symbol
ICK
T
T
T
T
T
IOGSRQ
T
T
T
F
IFNCTL
T
T
T
T
F5INY
T
BYYB
CKLO
RPW
IF5X
IF6Y
CKO
TOG
ILO
IF5
CH
RQ
CL
/ T
/ T
/ T
/ T
/ T
/ T
/ T
R
CKI
CKIF5
CKF5IN
CKIF6
CKDI
CKCE
CKR
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
Incremental delay routing through transparent latch
to XQ/YQ outputs
BY input to YB output
FF clock CLK to XQ/YQ outputs
Latch clock CLK to XQ/YQ outputs
4-input function: F/G inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
CE input
SR/BY inputs (synchronous)
Minimum pulse width, High
Minimum pulse width, Low
Minimum pulse width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Delay from GSR to XQ/YQ outputs
Toggle frequency (for export control)
Description
(1)
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Spartan-II FPGA Family: DC and Switching Characteristics
1.3 / 0
1.6 / 0
1.0 / 0
1.6 / 0
0.8 / 0
0.9 / 0
0.8 / 0
Min
3.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Max
263
Speed Grade
0.6
0.7
0.9
1.0
0.4
0.7
0.6
1.1
1.2
1.9
1.9
1.1
9.9
-
-
-
-
-
-
-
-
1.4 / 0
1.8 / 0
1.1 / 0
1.8 / 0
0.8 / 0
0.9 / 0
0.8 / 0
Min
3.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max
11.7
263
0.7
0.9
1.1
1.1
0.4
0.9
0.7
1.3
1.5
1.9
1.9
1.3
-
-
-
-
-
-
-
-
Module 3 of 4
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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