XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 33

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Table 11: Available Library Primitives
Port Signals
Each block RAM port operates independently of the others
while accessing the same set of 4096 memory cells.
Table 12
block RAM memory.
Table 12: Block RAM Port Aspect Ratios
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time
referenced to the CLK pin.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the
memory cells.
Write Enable—WE[A|B]
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the
contents of the memory cells referenced by the address bus
reflect on the data out bus.
DS001-2 (v2.8) June 13, 2008
Product Specification
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
RAMB4_S16_S16
Width
16
1
2
4
8
Primitive
describes the depth and width aspect ratios for the
R
Depth
4096
2048
1024
512
256
Port A Width
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
ADDR Bus
16
4
8
Port B Width
DATA<15:0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
Data Bus
DATA<0>
N/A
N/A
N/A
16
16
16
4
8
8
www.xilinx.com
Reset—RST[A|B]
The reset pin forces the data output bus latches to zero
synchronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
Address Bus—ADDR[A|B]<#:0>
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width,
as shown in
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
Address Mapping
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port. The physical RAM location addressed for a particular
width are described in the following formula (of interest only
when the two ports use different aspect ratios).
Table 13
width.
Table 13: Port Address Mapping
Widt
Port
16
h
1
2
4
8
Spartan-II FPGA Family: Functional Description
shows low order address mapping for each port
4095... 1
2047...
1023...
511...
255...
Start = ([ADDR
Table
End = ADDR
Table
12.
5
07
1
4
03
12.
1
3
06
port
1
2
01
Addresses
port
+ 1] * Width
1
1
05
Table
Port
1
0
02
* Width
0
9
04
12.
0
8
00
0
7
port
03
port
0
6
01
) – 1
0
5
02
Module 2 of 4
0
4
00
0
3
01
0
2
00
0
1
00
33
0
0