XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 43

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 18
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to
power/ground pairs for each Spartan-II device and package
combination.
Table 18: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
DS001-2 (v2.8) June 13, 2008
Product Specification
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS2
PCI
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
Table 19
provides the guidelines for the maximum number
R
Standard
for the number of effective output
CS, FG
68
41
29
22
17
14
40
24
17
13
10
10
18
15
9
8
5
8
4
4
9
5
Package
TQ, VQ
PQ,
36
20
15
12
21
12
9
7
5
9
7
5
4
3
5
4
4
4
9
5
3
8
www.xilinx.com
Table 18: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
Table 19: Effective Output Power/Ground Pairs for
Spartan-II Devices
Termination Examples
Creating a design with the Versatile I/O features requires
the instantiation of the desired library primitive within the
design code. At the board level, designers need to know the
termination techniques required for each I/O standard.
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the Versatile I/O
features. For a full range of accepted values for the DC
voltage specifications for each standard, refer to the table
associated with each figure.
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
Notes:
1.
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
AGP
VQ100
CS144
TQ144
PQ208
FG256
FG456
Pkg.
This analysis assumes a 35 pF load for each output.
Spartan-II FPGA Family: Functional Description
XC2S
12
12
15
8
-
-
-
Standard
XC2S
12
12
16
30
8
-
-
Spartan-II Devices
XC2S
12
16
16
50
-
-
-
XC2S
100
12
16
16
48
-
-
CS, FG
10
11
14
7
9
XC2S
Package
150
16
16
48
-
-
-
Module 2 of 4
TQ, VQ
PQ,
XC2S
200
5
6
4
7
5
16
16
48
-
-
-
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