XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 62

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

DLL Timing Parameters
All devices are 100 percent functionally tested. Because of
the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were
determined through statistical measurement at the package
pins using a clock mirror configuration and matched drivers.
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
2.
3.
4.
5.
T
Symbol
T
T
T
T
T
T
T
PHOOM
OJITCC
PHIOM
IJITCC
IPTOL
PHOO
LOCK
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
PHIO
T
T
F
F
Symbol
DLLPWHF
DLLPWLF
CLKINHF
CLKINLF
R
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
Output jitter (cycle-to-cycle) for any DLL clock output
Phase offset between CLKIN and CLKO
Phase offset between clock outputs on the DLL
Maximum phase difference between CLKIN and CLKO
Maximum phase difference between clock outputs on the DLL
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width (CLKDLLHF)
Input clock pulse width (CLKDLL)
Description
Description
(2)
www.xilinx.com
Spartan-II FPGA Family: DC and Switching Characteristics
(3)
timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Figure 52, page
parameters in the table below.
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
Min
> 60 MHz
2.0
2.5
60
25
(1)
F
(4)
CLKIN
-6
(5)
Max
200
100
Speed Grade
-
-
63, provides definitions for various
CLKDLLHF
Min
-
-
-
-
-
-
-
-
-
-
-
-
±150
±100
±140
±160
±200
Max
±60
Min
2.4
3.0
1.0
60
25
20
-
-
-
-
-5
Min
CLKDLL
-
-
-
-
-
-
-
-
-
-
-
-
Max
180
90
-
-
±300
±200
±100
±140
±160
Max
±60
120
1.0
20
25
50
90
Module 3 of 4
Units
MHz
MHz
Units
ns
ns
ns
ps
μs
μs
μs
μs
μs
ps
ps
ps
ps
ps
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