XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 40

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF primitive names is as follows.
<slew_rate> is either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24). The default is slew rate limited with 12 mA drive.
OBUF placement restrictions require that within a given
V
voltage. Input buffers of any type and output buffers that do
not require V
Table 17
The LOC property can specify a location for the OBUF.
Table 17: Output Standards Compatibility
Requirements
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure
bidirectional I/O.
With no extension or property specified for the generic
OBUFT primitive, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUFT can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
LVTTL 3-state output buffers have selectable drive
strengths.
The format for LVTTL OBUFT primitive names is as follows.
DS001-2 (v2.8) June 13, 2008
Product Specification
CCO
Rule 1
Rule 2
V
3.3
2.5
1.5
CCO
bank each OBUF share the same output source drive
39, typically implements 3-state outputs or
summarizes the output compatibility requirements.
OBUFT_<slew_rate>_<drive_strength>
OBUF_<slew_rate>_<drive_strength>
Only outputs with standards which share
compatible V
bank.
There are no placement restrictions for outputs
with standards that do not require a V
Compatible Standards
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
R
CCO
can be placed within any V
CCO
may be used within the same
CCO
CCO
bank.
.
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<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The Versatile I/O OBUFT placement restrictions require
that within a given V
output source drive voltage. Input buffers of any type and
output buffers that do not require V
the same V
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate primitive to the output net of the OBUFT
(PULLUP, PULLDOWN, or KEEPER).
The weak "keeper" circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a V
placement of a V
with a weak "keeper" circuit. This restriction does not affect
most circuit design as applications using an OBUFT
configured with a weak "keeper" typically implement a
bidirectional I/O. In this case the IBUF (and the
corresponding V
The LOC property can specify a location for the OBUFT.
IOBUF
Use the IOBUF primitive for bidirectional signals that
require both an input buffer and a 3-state output buffer with
an active high 3-state pin. The generic input/output buffer
IOBUF appears in
With no extension or property specified for the generic
IOBUF primitive, the assumed standard is LVTTL input
buffer and slew rate limited LVTTL with 12 mA drive strength
for the output buffer.
The LVTTL IOBUF can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF primitive names is as follows:
Figure 39: 3-State Output Buffer Primitive (OBUFT
Spartan-II FPGA Family: Functional Description
CCO
bank.
REF
REF
Figure
CCO
) are explicitly placed.
T
in the bank with an OBUFT configured
I
bank each OBUFT share the same
40.
IOBUFT
DS001_39_032300
REF
IO
CCO
have automatic
can be placed within
Module 2 of 4
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