XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 2

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

DS001-1 (v2.8) June 13, 2008
Introduction
The Spartan
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
•
Table 1: Spartan-II FPGA Family Members
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-1 (v2.8) June 13, 2008
Product Specification
Notes:
1.
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
Second generation ASIC replacement technology
-
-
-
-
-
All user I/O counts do not include the four global clock/user input pins. See details in
Densities as high as 5,292 logic cells with up to
200,000 system gates
Streamlined features based on Virtex
architecture
Unlimited reprogrammability
Very low cost
Cost-effective 0.18 micron process
®
-II Field-Programmable Gate Array family
Logic
1,728
2,700
3,888
5,292
Cells
432
972
(Logic and RAM)
R
System Gates
100,000
150,000
200,000
15,000
30,000
50,000
Table
1. System
®
FPGA
(R x C)
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
6
8 x 12
Array
CLB
www.xilinx.com
0
Spartan-II FPGA Family:
Introduction and Ordering
Information
Product Specification
•
•
•
•
CLBs
1,176
Total
216
384
600
864
96
System level features
-
-
-
-
-
-
-
-
-
-
-
Versatile I/O and packaging
-
-
-
-
-
-
Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx
system
-
SelectRAM™ hierarchical memory:
·
·
·
Fully PCI compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution
nets
IEEE 1149.1 compatible boundary scan logic
Pb-free package options
Low-cost packages available in all densities
Family footprint compatibility in common packages
16 high-performance interface standards
Hot swap Compact PCI friendly
Zero hold time simplifies system timing
Fully automatic mapping, placement, and routing
User I/O
Maximum
Available
16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
176
176
260
284
86
92
Table 2, page
(1)
Distributed RAM
13,824
24,576
38,400
55,296
75,264
6,144
4.
Total
Bits
®
ISE
®
development
Block RAM
Module 1 of 4
Total
Bits
16K
24K
32K
40K
48K
56K
2