XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 57

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
1
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
Data Input Delay Adjustments
T
T
T
T
Symbol
ILVCMOS2
T
T
T
T
T
IPCI33_3
IPCI33_5
IPCI66_3
T
T
T
ISSTL2
ISSTL3
ILVTTL
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table
IGTLP
IHSTL
IAGP
IGTL
ICTT
R
Standard-specific data input delay
adjustments
Description
www.xilinx.com
LVTTL
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
GTL
GTL+
HSTL
SSTL2
SSTL3
CTT
AGP
Spartan-II FPGA Family: DC and Switching Characteristics
Standard
(1)
"Delay Measurement Methodology," page
–0.04
–0.11
–0.11
–0.08
–0.04
–0.06
0.26
0.20
0.11
0.03
0.02
-6
0
Speed Grade
–0.05
–0.13
–0.13
–0.09
–0.05
–0.07
0.30
0.24
0.13
0.04
0.02
-5
0
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60.
57