XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 96

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XC2S100E-7PQ208C

Manufacturer Part Number

XC2S100E-7PQ208C

Description

100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN

Manufacturer

Xilinx, Inc.

Datasheet

1.XC2S100E-7PQ208C.pdf (99 pages)

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XC2S200 Device Pinouts (Continued)

DS001-4 (v2.8) June 13, 2008

Product Specification

V

V

I/O (D5)

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

GND

V

I/O, V

I/O (D4)

I/O

I/O

I/O

I/O

V

I/O, TRDY

V

V

GND

I/O, IRDY

I/O

I/O

I/O

I/O

I/O

I/O (D3)

I/O, V

V

GND

I/O

I/O

CCO

CCINT

CCO

CCINT

CCO

CCO

CCO

XC2S200 Pad Name

Function

REF

REF

(1)

(1)

R

Bank

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

2

2

2

2

2

2

2

2

2

2

2

2

-

-

-

-

-

-

PQ208

P117

P118

P120

P121

P123

P125

P126

P127

P128

P129

P130

P130

P132

P133

P134

P136

P119

P122

P124

P131

P135

P137

P138

P139

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Bank 3*

V

Bank 3*

V

Bank 3*

Bank 2*

Bank 2*

FG256

GND*

GND*

GND*

GND*

V

V

V

V

V

CCINT

CCINT

M16

K14

K13

K12

K16

K15

H16

H14

H15

G16

H13

G14

G15

L16

L15

J16

J14

J15

J13

CCO

CCO

CCO

CCO

CCO

-

-

-

-

-

-

-

-

*

*

Bank 3*

V

Bank 3*

V

Bank 3*

Bank 2*

Bank 2*

FG456

GND*

GND*

GND*

GND*

V

V

V

V

V

CCINT

CCINT

M17

M19

M20

M18

M22

R21

P18

R22

P19

P20

P21

N19

P22

N18

N20

N21

N22

K19

K20

K21

K22

L20

L17

L18

L21

L22

J21

CCO

CCO

CCO

CCO

CCO

*

*

Bndry

Scan

833

836

839

842

845

848

851

854

857

860

863

866

872

875

878

881

890

893

896

902

905

908

911

917

920

923

926

www.xilinx.com

-

-

-

-

-

-

-

-

-

-

-

XC2S200 Device Pinouts (Continued)

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O (D2)

V

V

GND

I/O (D1)

I/O, V

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O, V

V

GND

I/O

I/O

GND

I/O

I/O

I/O, V

GND

I/O

I/O

I/O

I/O (DIN, D0)

I/O (DOUT,

BUSY)

CCLK

V

CCINT

CCO

CCO

CCO

XC2S200 Pad Name

Function

REF

REF

REF

Bank

Spartan-II FPGA Family: Pinout Tables

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

-

-

-

-

-

-

-

PQ208

P140

P141

P142

P143

P144

P145

P146

P147

P148

P149

P150

P151

P152

P153

P154

P155

P156

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

V

Bank 2*

Bank 2*

Bank 2*

FG256

GND*

GND*

GND*

GND*

GND*

GND*

V

V

V

CCINT

G12

G13

E16

D16

E15

E14

C16

E13

B16

D14

C15

D15

F16

F15

F14

F12

F13

CCO

CCO

CCO

-

-

-

-

-

-

-

-

-

-

-

*

V

Bank 2*

Bank 2*

Bank 2*

FG456

GND*

GND*

GND*

GND*

GND*

GND*

V

V

V

CCINT

G21

G18

G20

G19

K18

H21

H19

H20

H22

H18

E22

E21

D22

E20

D21

C22

D20

C21

B22

J20

J18

J22

J19

F22

F19

F21

F20

F18

CCO

CCO

CCO

Module 4 of 4

*

Bndry

Scan

1001

1004

1007

1013

1016

1019

929

932

935

938

941

944

947

950

953

956

962

965

968

971

974

977

980

983

986

989

995

998

-

-

-

-

-

-

-

-

-

-

96

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