XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 7

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

DS001-2 (v2.8) June 13, 2008
Architectural Description
Spartan-II FPGA Array
The Spartan
Figure
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As can be seen in
structure with easy access to all support and routing
structures. The IOBs are located around all the logic and
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DS001-2 (v2.8) June 13, 2008
Product Specification
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
2, is composed of five major configurable elements:
®
-II field-programmable gate array, shown in
Figure
TFF
OFF
IFF
2, the CLBs form the central logic
R
Figure 2: Spartan-II FPGA Input/Output Block (IOB)
50
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Spartan-II FPGA Family:
Functional Description
Product Specification
memory elements for easy and quick routing of signals on
and off the chip.
Values stored in static memory cells control all the
configurable logic elements and interconnect resources.
These values load into the memory cells on power-up, and
can reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the
following sections.
Input/Output Block
The Spartan-II FPGA IOB, as seen in
inputs and outputs that support a wide variety of I/O
signaling standards. These high-speed inputs and outputs
are capable of supporting various state of the art memory
and bus interfaces.
which are supported along with the required reference,
output and termination voltages needed to meet the
standard.
Table 3
lists several of the standards
Figure
2, features
Module 2 of 4
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