XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 19

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Notes: (referring to waveform above:)
1.
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low. At this time, the user can
delay configuration by holding either PROGRAM or INIT
Low, which causes the device to remain in the memory
clearing phase. Note that the bidirectional INIT line is
driving a Low logic level during memory clearing. To avoid
contention, use an open-drain driver to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the
configuration data are discussed in the sections treating the
configuration modes individually. The sequence of
operations necessary to load configuration data using the
serial modes is shown in
Slave Parallel mode is shown in
CRC Error Checking
During the loading of configuration data, a CRC value
embedded in the configuration file is checked against a
CRC value calculated within the FPGA. If the CRC values
DS001-2 (v2.8) June 13, 2008
Product Specification
Before configuration can begin, V
R
.
PROGRAM
T
T
T
T
POR
PL
ICCK
PROGRAM
Symbol
V
INIT
CC
Figure
(1)
14. Loading data using the
Figure 19, page
Power-on reset
Program latency
CCLK output delay (Master Serial mode only)
Program pulse width
CCINT
Figure 12: Configuration Timing on Power-Up
must be greater than 1.6V and V
25.
Description
CCLK Output or Input
www.xilinx.com
T
POR
M0, M1, M2
(Required)
do not match, the FPGA drives INIT Low to indicate that a
frame error has occurred and configuration is aborted.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See
Configuration
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the
configuration data, initiates the sequence.
During start-up, the device performs four operations:
1. The assertion of DONE. The failure of DONE to go High
2. The release of the Global Three State net. This
3. Negates Global Set Reset (GSR). This allows all
4. The assertion of Global Write Enable (GWE). This
T
PL
may indicate the unsuccessful loading of configuration
data.
activates I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-down resistors present.
flip-flops to change state.
allows all RAMs and flip-flops to change state.
CCO
Spartan-II FPGA Family: Functional Description
Bank 2 must be greater than 1.0V.
Memory".
T
ICCK
300 ns
Valid
0.5
Min
-
-
μ
s
DS001_12_102301
100
2 ms
Max
4
-
μ
s
μ
s
"Clearing
Module 2 of 4
19