XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 37

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

support of a wide variety of applications, from general
purpose standard applications to high-speed low-voltage
memory busses.
Versatile I/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL
output buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak "keeper" circuit ideal for
use in external bussing applications.
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
The input buffer has an optional delay element used to
guarantee a zero hold time requirement for input signals
registered within the IOB.
The Versatile I/O features also provide dedicated resources
for input reference voltage (V
voltage (V
that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the Versatile I/O features,
system-level design and board design can be greatly
simplified and improved.
Fundamentals
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored
specifically to the needs of that application. The bus I/O
standards provide specifications to other vendors who
create products designed to interface with these
applications. Each standard often has its own specifications
for current, voltage, I/O buffering, and termination
techniques.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly
dependent on the capability of the programmable logic
device to support an ever increasing variety of I/O
standards
The Versatile I/O resources feature highly configurable
input and output buffers which provide support for a wide
variety of I/O standards. As shown in
type can support a variety of voltage requirements.
DS001-2 (v2.8) June 13, 2008
Product Specification
CCO
R
), along with a convenient banking system
REF
) and output source
Table
15, each buffer
www.xilinx.com
Table 15: Versatile I/O Supported Standards (Typical
Values)
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Spartan-II devices.
While most I/O standards specify a range of allowed
voltages, this document records typical voltage values only.
Detailed information on each specification may be found on
the Electronic Industry Alliance JEDEC website at
http://www.jedec.org
and termination application examples, see
SelectIO Interfaces in Spartan-II and Spartan-IIE FPGAs."
LVTTL — Low-Voltage TTL
The Low-Voltage TTL (LVTTL) standard is a general
purpose EIA/JESDSA standard for 3.3V applications that
uses an LVTTL input buffer and a Push-Pull output buffer.
This standard requires a 3.3V output source voltage
(V
(V
LVCMOS2 — Low-Voltage CMOS for 2.5V
The Low-Voltage CMOS for 2.5V or lower (LVCMOS2)
standard is an extension of the LVCMOS standard (JESD
8.5) used for general purpose 2.5V applications. This
standard requires a 2.5V output source voltage (V
does not require the use of a reference voltage (V
board termination voltage (V
LVTTL (2-24 mA)
LVCMOS2
PCI (3V/5V,
33 MHz/66 MHz)
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I
and II
SSTL2 Class I
and II
CTT
AGP-2X
CCO
REF
I/O Standard
) or a termination voltage (V
), but does not require the use of a reference voltage
Spartan-II FPGA Family: Functional Description
. For more details on the I/O standards
Reference
Voltage
(V
Input
0.75
1.25
1.32
N/A
N/A
N/A
0.8
1.0
0.9
0.9
1.5
1.5
REF
TT
)
).
TT
Voltage
Source
Output
(V
).
N/A
N/A
3.3
2.5
3.3
1.5
1.5
1.5
3.3
2.5
3.3
3.3
CCO
)
XAPP179
Termination
Module 2 of 4
Voltage
Board
(V
CCO
REF
0.75
1.25
N/A
N/A
N/A
N/A
1.2
1.5
1.5
1.5
1.5
1.5
, "Using
TT
) or a
), but
)
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