XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 50

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Revision History
DS001-2 (v2.8) June 13, 2008
Product Specification
09/18/00
03/05/01
09/03/03
06/13/08
Date
R
Version
2.0
2.1
2.2
2.8
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
Clarified guidelines for applying power to V
The following changes were made:
•
•
•
•
•
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
"Serial Modes," page 20
Maximum V
In
In
In
port.
"Boundary Scan," page
Table 9, page
"Slave Parallel Mode," page
IH
values in
17, added note about the state of I/Os after power-on.
www.xilinx.com
Figure 15
Table 32
cautions about toggling WRITE during serial configuration.
13, removed sentence about lack of INTEST support.
and
23, explained configuration bit alignment to SelectMap
and
Description
Figure 18
Table 33
Spartan-II FPGA Family: Functional Description
CCINT
and V
changed to 5.5V.
since Mode pins can be pulled up to either
CCO
Module 2 of 4
50