ata6616 ATMEL Corporation, ata6616 Datasheet - Page 129

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.11.11.7
4.11.11.8
9132A–AUTO–10/08
DRAFT
Timer/Counter0 Interrupt Flag Register – TIFR0
General Timer/Counter Control Register – GTCCR
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the ATtiny167 and will always read as zero.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt
Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0A (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
• Bit 1 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter0 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the
chronization Mode” on page 132
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TSM
R/W
7
0
R
7
–
0
R
6
–
0
R
6
–
0
for a description of the Timer/Counter Synchronization mode.
ATA6616/ATA6617 [Preliminary]
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
“Bit 7 – TSM: Timer/Counter Syn-
R
2
–
0
R
2
–
0
OCF0A
R/W
PSR0
1
0
R/W
1
0
TOV0
R/W
PSR1
R/W
0
0
0
0
GTCCR
TIFR0
129