ata6616 ATMEL Corporation, ata6616 Datasheet - Page 64

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.5.5.3
64
ATA6616/ATA6617 [Preliminary]
CLKCSR – Clock Control & Status Register
Table 4-13.
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The
CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to zero.
CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits are writ-
ten. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny167 and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’
command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is stable.
The delay from the request and the flag setting is not fixed, it depends on the clock start-up time,
the clock frequency and, of course, if the clock is alive. The user’s code has to differentiate
between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition.
Bit
Read/Write
Initial Value
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKCCE
Clock Prescaler Select
R/W
7
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
5
–
0
CLKRDY
R
4
0
CLKPS0
DRAFT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKC3
R/W
3
0
CLKC2
R/W
2
0
Clock Division Factor
CLKC1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
128
256
16
32
64
1
2
4
8
CLKC0
R/W
9132A–AUTO–10/08
0
0
CLKCSR