ata6616 ATMEL Corporation, ata6616 Datasheet - Page 233

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.18.11.4
9132A–AUTO–10/08
DRAFT
ADCSRB – ADC Control and Status Register B
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7– BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected
by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions
are supported and the voltage on the positive input must always be larger than the voltage on
the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode
two-sided conversions are supported and the result is represented in the two’s complement
form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +
1 sign bit.
• Bit 3 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to zero
when ADCSRB register is written.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA register is written to one, the value of these bits selects which source will
trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A con-
version will be triggered by the rising edge of the selected Interrupt Flag. Note that switching
from a trigger source that is cleared to a trigger source that is set, will generate a positive edge
on the trigger signal. If ADEN in ADCSRA register is set, this will start a conversion. Switching to
Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag
is set
Bit
Read/Write
Initial Value
.
227.
R/W
BIN
7
0
ACME
R/W
6
0
ACIR1
ATA6616/ATA6617 [Preliminary]
R/W
5
0
ACIR0
R/W
4
0
R
3
–
0
ADTS2
R/W
2
0
“ADC Conversion Result” on
ADTS1
R/W
1
0
ADTS0
R/W
0
0
ADCSRB
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