ata6616 ATMEL Corporation, ata6616 Datasheet - Page 171

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.14.2.4
4.14.2.5
4.14.3
9132A–AUTO–10/08
DRAFT
Data Modes
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATtiny167 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATtiny167 is also used for program memory and EEPROM download-
ing or uploading. See
and verification.
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
4-60
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 4-40
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
and
Figure
and
SPD7
Table
SPIF
R/W
4-61. Data bits are shifted out and latched in on opposite edges of the SCK sig-
X
R
7
7
0
4-41, as done below:
Section 4.22.8 “Serial Downloading” on page 262
Table
WCOL
SPD6
R/W
R
6
X
6
0
4-42). This means that the minimum SCK period will be two CPU
SPD5
ATA6616/ATA6617 [Preliminary]
R/W
X
R
5
5
–
0
SPD4
R/W
X
4
R
4
–
0
SPD3
R/W
X
R
3
3
–
0
SPD2
R/W
X
2
R
2
–
0
SPD1
R/W
1
X
R
1
–
0
for serial programming
SPD0
SPI2X
R/W
R/W
X
0
0
0
SPDR
Undefined
SPSR
Figure
clkio
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