ata6616 ATMEL Corporation, ata6616 Datasheet - Page 146
ata6616
Manufacturer Part Number
ata6616
Description
Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
Manufacturer
ATMEL Corporation
Datasheet
1.ATA6616.pdf
(310 pages)
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4.13.8.1
4.13.8.2
146
ATA6616/ATA6617 [Preliminary]
Compare Output Function
Compare Output Mode and Waveform Generation
Figure 4-49. Compare Match Output Logic
The general I/O port function is overridden by the Output Compare (OC1A/B) from the Wave-
form Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit is set in
TCCR1D register. However, the OC1A/Bi pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1A/Bi
pin (DDR_OC1A/Bi) must be set as output before the OC1A/B value is visible on the pin. The
port override function is generally independent of the Waveform Generation mode, but there are
some exceptions. Refer to
The design of the Output Compare pin logic allows initialization of the OC1A/B state before the
output is enabled. Note that some COM1A/B1:0 bit settings are reserved for certain modes of
operation.
The COM1A/B1:0 bits have no effect on the Input Capture unit.
The Waveform Generator uses the COM1A/B1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM1A/B1:0 = 0 tells the Waveform Generator that no action
on the OC1A/B Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 4-35 on page
Table 4-36 on page
A change of the COM1A/B1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC1A/B strobe bits.
See “16-bit Timer/Counter Register Description” on page 157.
COMnx1
COMnx0
FOCnx
clk
I/O
158.
158, and for phase correct and phase and frequency correct PWM refer to
Table
Waveform
Generator
4-34,
OCnxi
Table 4-35
Table 4-34 on page
D
D
PORT
D
DDR
OCnx
Q
Q
Q
DRAFT
and
Table 4-36
1
0
157. For fast PWM mode refer to
for details.
OCnxi
Pin
9132A–AUTO–10/08
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