ata6616 ATMEL Corporation, ata6616 Datasheet - Page 175

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

Figure 4-64. Three-wire Mode, Timing Diagram
4.15.3.2
9132A–AUTO–10/08
DRAFT
CYCLE
SPI Master Operation Example
USCK
USCK
DO
DI
( Reference )
A
The Three-wire mode timing is shown in
erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI
is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative
edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-
ples data at negative and changes the output at positive edges. The USI clock modes
corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram
The following code demonstrates how to use the USI module as a SPI Master:
1. The Slave device and Master device sets up its data output and, depending on the pro-
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
B
MSB
SPITransfer:
tocol used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the USI Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port Data Direction Register. Note that point A and B
does not have any specific order, but both must be at least one half USCK cycle before
point C where the data is sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on
the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit
counter will count both edges.
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is set
to Idle mode. Depending of the protocol used the slave device can now set its output to
high impedance.
MSB
C
1
sts
ldi
sts
ldi
D
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
2
6
6
3
5
5
(Figure
ATA6616/ATA6617 [Preliminary]
4
4
4
4-64), a bus transfer involves the following steps:
Figure 4-64
5
3
3
6
2
2
At the top of the figure is a USCK cycle ref-
7
1
1
LSB
LSB
8
E
175