ata6616 ATMEL Corporation, ata6616 Datasheet - Page 245

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.21.2.2
4.21.2.3
9132A–AUTO–10/08
DRAFT
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10 0001
or “00 0001
Note:
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction
is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the
value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will
auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within
three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and
SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. See
description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See
Bit
Rd (Z=0x0001)
Bit
Rd (Z=0x0000)
Only one SPM instruction should be active at any time.
Table 4-69 on page 251
b
” in the lower six bits will have no effect.
FLB7
7
–
7
FLB6
6
6
–
ATA6616/ATA6617 [Preliminary]
FLB5
5
–
5
for detailed description and mapping of the Fuse High byte.
FLB4
b
4
–
4
”, “01 0001
FLB3
3
–
3
Table 4-70 on page 252
b
”, “00 1001
FLB2
2
–
2
b
”, “00 0101
FLB1
LB2
1
1
FLB0
LB1
0
0
b
for a detailed
”, “00 0011
245
b
”