ata6616 ATMEL Corporation, ata6616 Datasheet - Page 204

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.16.5.16
204
ATA6616/ATA6617 [Preliminary]
OCD Support
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O
view behavior in AVR Studio)
Note:
1. LINCR:
2. LINSIR:
3. LINENR:
4. LINERR:
5. LINBTR:
6. LINBRRH & LINBRRL:
7. LINDLR:
8. LINIDR:
9. LINSEL:
10. LINDAT:
– LINCR[6..0] are R/W accessible,
– LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
– LIDST[2..0] and LBUSY are always Read accessible,
– LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly
– Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR
– All bits are R/W accessible.
– All bits are R/W accessible,
– Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
– LBT[5..0] are R/W access only if LDISR is set,
– If LDISR is reset, LBT[5..0] are unchangeable.
– All bits are R/W accessible.
– All bits are R/W accessible.
– LID[5..0] are R/W accessible,
– LP[1..0] are Read accessible and are always updated on the fly.
– All bits are R/W accessible.
– All bits are in R/W accessible,
– Note that LAINC has no more effect on the auto-incrementation and the access to
by writing 1 or 0).
bits.
the full FIFO is done setting LINDX[2..0] of LINSEL.
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
DRAFT
9132A–AUTO–10/08