ata6616 ATMEL Corporation, ata6616 Datasheet - Page 36

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.3.5.1
4.3.6
36
ATA6616/ATA6617 [Preliminary]
Instruction Execution Timing
SPH and SPL – Stack Pointer Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-5
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-6.
Bit
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
Total Execution Time
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Result Write Back
SP15
R/W
R/W
SP7
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
15
7
clk
clk
SP14
CPU
SP6
R/W
R/W
CPU
14
6
SP13
SP5
R/W
R/W
13
CPU
5
T1
T1
, directly generated from the selected clock source for the
SP12
R/W
R/W
SP4
12
4
DRAFT
T2
SP11
T2
SP3
R/W
R/W
11
3
SP10
SP2
R/W
R/W
10
2
T3
T3
R/W
R/W
SP9
SP1
9
1
9132A–AUTO–10/08
T4
T4
SP8
SP0
R/W
R/W
8
0
SPH
SPL