ata6616 ATMEL Corporation, ata6616 Datasheet - Page 209

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.16.6.5
4.16.6.6
9132A–AUTO–10/08
DRAFT
LIN Bit Timing Register - LINBTR
LIN Baud Rate Register - LINBRR
• Bit 2 - LPERR: Parity Error Flag
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
Initial Value
Read/Write
Initial Value
Read/Write
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
sample-time = (1 /
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINBRR is written.
The LDIV value is used to scale the entering clk
UART baud rate.
Bit
Bit
Bit
– 0 = No error,
– 1 = Parity error.
– 0 = No error,
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
LDISR
LDIV7
R/W
R/W
15
7
0
7
0
-
f
clk
LDIV6
R/W
14
R
6
0
-
6
0
-
i/o
) x (LDIV[11..0] + 1)
R/(W)
LBT5
LDIV5
R/W
ATA6616/ATA6617 [Preliminary]
13
5
1
5
0
-
i/o
R/(W)
LBT4
LDIV4
R/W
Frequency
12
4
0
4
0
-
R/(W)
LDIV11
LBT3
LDIV3
R/W
3
0
11
i/o
3
0
frequency to achieve appropriate LIN or
LBT2
R/(W)
LDIV10
LDIV2
R/W
2
0
10
0
2
R/(W)
LBT1
LDIV1
LDIV9
R/W
1
0
1
9
0
R/(W)
LBT0
LDIV0
LDIV8
R/W
0
0
0
8
0
LINBTR
LINBRRL
LINBRRH
209