ata6616 ATMEL Corporation, ata6616 Datasheet - Page 179

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

Figure 4-66. Two-wire Mode, Typical Timing Diagram
9132A–AUTO–10/08
DRAFT
SDA
SCL
A B
S
C
ADDRESS
Referring to the timing diagram
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 4-67. Start Condition Detector, Logic Diagram
1 - 7
1. The a start condition is generated by the Master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the Master has forced an
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that the
USI Data Register bit must be set to one for the output to be enabled. The slave
device’s start detector logic (Figure 4-67.) detects the start condition and sets the
USISIF Flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the Slave to wake up from sleep or complete
its other tasks before setting up the USI Data Register to receive the address. This is
done by clearing the start condition flag and reset the counter.
samples the data and shift it into the USI Data Register at the positive edge of the SCL
clock.
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the Master has addressed, it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14
before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its
output. If the bit is set, a master read operation is in progress (i.e., the slave drives the
SDA line) The slave can hold the SCL line low after the acknowledge (E).
given by the Master (F). Or a new start condition is given.
R/W
8
Write( USISIF)
D
SDA
SCL
ACK
9
E
(Figure
ATA6616/ATA6617 [Preliminary]
DATA
1 - 8
4-66), a bus transfer involves the following steps:
ACK
9
D Q
CLR
DATA
1 - 8
D Q
CLR
ACK
USISIF
CLOCK
HOLD
9
P
F
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