ata6616 ATMEL Corporation, ata6616 Datasheet - Page 255
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ata6616
Manufacturer Part Number
ata6616
Description
Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
Manufacturer
ATMEL Corporation
Datasheet
1.ATA6616.pdf
(310 pages)
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4.22.7
4.22.7.1
4.22.7.2
4.22.7.3
9132A–AUTO–10/08
DRAFT
Parallel Programming
Enter Programming Mode
Considerations for Efficient Programming
Chip Erase
Table 4-76.
The following algorithm puts the device in parallel programming mode:
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
The Chip Erase will erase the Flash and EEPROM
are not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note:
1. Apply 4.5 - 5.5V between Vcc and GND.
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in
4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
5. Wait at least 50 µs before sending a new command.
• The command needs only be loaded once when writing or reading multiple memory
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
• Address high byte needs only be loaded before programming or reading a new 256 word
locations.
EESAVE Fuse is programmed) and Flash after a Chip Erase.
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
Command Byte
100 ns.
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
1000 0000
0100 0000
0010 0000
0001 0000
0001 0001
0000 1000
0000 0100
0000 0010
0000 0011
The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Command Byte Bit Coding
b
b
b
b
b
b
b
b
b
Command Executed
Chip Erase
Write Fuse bits
Write Lock bits
Write Flash
Write EEPROM
Read Signature bytes and Calibration byte
Read Fuse and Lock bits
Read Flash
Read EEPROM
ATA6616/ATA6617 [Preliminary]
Table 4-74 on page 254
(Note:)
memories plus Lock bits. The Lock bits
to “0000
b
” and wait at least
255
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