atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 16

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

3.6
3.7
16
Stack Pointer
Instruction Execution Timing
ATmega32/64/M1/C1
Figure 3-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Bit
Read/Write
Initial Value
X-register
Y-register
Z-register
15
SP15
SP7
7
R/W
R/W
0
0
The X-, Y-, and Z-registers
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
14
SP14
SP6
6
R/W
R/W
0
0
13
SP13
SP5
5
R/W
R/W
0
0
XH
YH
ZH
0
CPU
12
SP12
SP4
4
R/W
R/W
0
0
, directly generated from the selected clock source for the
11
SP11
SP3
3
R/W
R/W
0
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
10
SP10
SP2
2
R/W
R/W
0
0
9
SP9
SP1
1
R/W
R/W
0
0
XL
YL
ZL
8
SP8
SP0
0
R/W
R/W
0
0
0
SPH
SPL
7647A–AVR–02/08
0
0
0
0
0