atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 35

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

5.6.2
5.7
5.8
7647A–AVR–02/08
128 kHz Internal Oscillator
External Clock
PLL Control and Status Register – PLLCSR
2.
3.
Figure 5-3.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega32/64/M1/C1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Bit
$29 ($29)
Read/Write
Initial Value
PLL
XTAL1
XTAL2
for Fast Peripherals. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
RC OSCILLATOR
OSCCAL
PCK Clocking System
R
7
–
0
OSCILLATORS
8 MHz
R
6
–
0
DIVIDE
R
5
–
0
BY 8
R
4
–
0
PLLE
PLL
64x
Detector
Lock
R
3
–
0
DIVIDE
DIVIDE
ATmega32/64/M1/C1
PLLF
BY 2
BY 4
PLLF
R/W
2
0
PLLE
R/W
0/1
1
CLK
PLOCK
CK
PLL
SOURCE
PLOCK
R
0
0
PLLCSR
Figure
35