atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 224

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

17.6.5
17.6.6
17.6.7
224
ATmega32/64/M1/C1
LIN Bit Timing Register - LINBTR
LIN Baud Rate Register - LINBRR
LIN Data Length Register - LINDLR
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
• Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length
Bit
Read/Write
Initial Value
Bit
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
written to zero when LINBRR is written.
UART baud rate.
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must be
The LDIV value is used to scale the entering clk
LTXDL3
LDISR
LDIV7
R/W
R/W
R/W
15
7
0
7
0
7
0
-
sample-time = (1 /
LTXDL2
LDIV6
R/W
R/W
14
R
6
0
6
0
6
0
-
-
LTXDL1
R/(W)
LDIV5
LBT5
R/W
R/W
13
5
1
5
0
5
0
-
i/o
f
LTXDL0
R/(W)
LBT4
LDIV4
clk
R/W
R/W
Frequency
12
4
0
4
0
4
0
-
i/o
) x (LDIV[11..0] + 1)
LRXDL3
R/(W)
LDIV11
LBT3
LDIV3
R/W
R/W
3
0
11
3
0
3
0
i/o
frequency to achieve appropriate LIN or
R/(W)
LRXDL2
LBT2
LDIV10
LDIV2
R/W
R/W
2
0
10
2
0
2
0
R/(W)
LRXDL1
LBT1
LDIV1
LDIV9
R/W
R/W
1
0
1
9
0
1
0
LRXDL0
R/(W)
LDIV0
LDIV8
LBT0
R/W
R/W
0
0
0
8
0
0
0
7647A–AVR–02/08
LINBRRL
LINBRRH
LINBTR
LINDLR