atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 34

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

5.6
5.6.1
34
PLL
ATmega32/64/M1/C1
Internal PLL
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre-
quency range 7.3 - 8.1 MHz.
The internal PLL in ATmega32/64/M1/C1 generates a clock frequency that is 64x multiplied from
nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC
Oscillator which is divided down to 1 MHz. See the
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register
will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC
Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency satu-
rates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be
noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1
MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only
when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is
set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep
modes
.
Table 5-7.
1.
RC Osc
Ext Osc
CKSEL
Ext Clk
0011
0101
0001
3..0
This value do not provide a proper restart ; do not use PD in this clock scheme
SUT1..0
Start-up Times when the PLL is selected as system clock
00
01
10
11
00
01
10
11
00
01
10
11
Start-up Time from Power-down
and Power-save
16K CK
16K CK
16K CK
6 CK
6 CK
6 CK
1K CK
1K CK
1K CK
1K CK
1K CK
(1)
(2)
(3)
Figure 5-3 on page
Reserved
Additional Delay from Reset
35.
14CK + 64 ms
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
14CK + 4 ms
(V
CC
14CK
14CK
14CK
14CK
= 5.0V)
7647A–AVR–02/08