atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 221

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

17.6.2
7647A–AVR–02/08
LIN Status and Interrupt Register - LINSIR
• Bit 3 - LENA: Enable
• Bit 2:0 - LCMD[2..0]: Command and mode
• Bits 7:5 - LIDST[2:0]: Identifier Status
• Bit 4 - LBUSY: Busy Signal
• Bit 3 - LERR: Error Interrupt
Bit
Read/Write
Initial Value
b. UART mode (default = 00):
enable bit - LENERR - is set in LINENIR.
– 10 = No Frame_Time_Out (listen mode “off” & CRC “on”),
– 11 = Listening mode (CRC “on” & Frame_Time_Out “on”).
– 00 = 8-bit, no parity (listen mode “off”),
– 01 = 8-bit, even parity (listen mode “off”),
– 10 = 8-bit, odd parity (listen mode “off”),
– 11 = Listening mode, 8-bit, no parity.
– 0 = Disable (both LIN and UART modes),
– 1 = Enable (both LIN and UART modes).
–000 = LIN Rx Header - LIN abort,
– 001 = LIN Tx Header,
– 010 = LIN Rx Response,
– 011 = LIN Tx Response,
– 100 = UART Rx & Tx Byte disable,
– 11x = UART Rx Byte enable,
– 1x1 = UART Tx Byte enable.
– 0xx = no specific identifier,
– 100 = Identifier 60 (0x3C),
– 101 = Identifier 61 (0x3D),
– 110 = Identifier 62 (0x3E),
– 111 = Identifier 63 (0x3F).
– 0 = Not busy,
– 1 = Busy (receiving or transmitting).
– 0 = No error,
The command is only available if LENA is set.
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective
LIDST2
R
7
0
LIDST1
R
6
0
LIDST0
R
5
0
LBUSY
R
4
0
R/W
LERR
3
0
one
ATmega32/64/M1/C1
R/W
LIDOK
2
0
one
R/W
LTXOK
1
0
one
LRXOK
R/W
0
0
one
LINSIR
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